EW31244SL7QV Datasheet, PDF (173/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3.8
Table 101.
SU IDE Device/Head Register - SUIDR
This SU IDE Device/Head Register is a read/write register. The content of the SU IDE
Device/Head Register is a command parameter. The content of this register must be loaded before
the SU IDE Command Register is written. The content of the SU IDE Device/Head Register is
command dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6)
Specification.
SU IDE Device/Head Register - SUIDHR
PCI
Attributes
7
4
0
rv rw rv rw rw rw rw rw
PCI IDE Mode BAR0/BAR2 Offset
= 06H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07
06
05
04
03-00
Reserved
Logical Addressing Mode - This bit indicates the addressing mode:
0 = CHS (Cylinder/Head/Sector) Mode
1 = LBA (Logical Block Addressing) Mode
Reserved
Device Device Select (DEV Bit) - This bit is used to select one of the two devices:
Dependent ^a _{0 = Device 0}
1 = Device 1
Head - This field is dependent on the device access methods. There are three methods:
• CHS Mode: In CHS mode, this field indicates the head number.
• 28-bit LBA Mode: This field is used for bit positions LBA[27:24] of the 28-bit addressing LBA[27:0].
• 48-bit LBA Mode: This field is reserved.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a diagnostic code. The diagnostic
code is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
Developer’s Manual
April 2004
173