EW31244SL7QV Datasheet, PDF (192/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.7 SU PCI DPA Mode Base Address Registers
This section defines the configuration registers that are different in PCI Direct Port Access mode.
5.10.7.1
Table 114.
SU PCI DPA Base Address Register 0 - SUPDBAR0
The SU PCI DPA Base Address Register 0 (SUDBAR0) together with the SU PCI DPA Upper
Base Address Register 0 (SUDUBAR0) defines the block of memory addresses in which the SATA
Ports registers are mapped.
SU PCI DPA Base Address Register 0 - SUDBAR0
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv ro ro ro ro
Bit
31:12
11:04
03
02:01
00
PCI Configuration Address Offset
10H -13H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
00000H
00H
0₂
10₂
0₂
Description
Base Address 0 - These bits define the actual location the SATA Unit is to respond to when addressed
from the PCI bus.
Reserved.
Prefetchable Indicator - When cleared, defines the memory space as non-prefetchable.
Type Indicator - Defines the width of the addressability for this memory window:
00 - Memory Window is locatable anywhere in 32 bit address space.
10 - Memory Window is locatable anywhere in 64 bit address space.
Memory Space Indicator - This bit field describes memory or I/O space base address. The SATA Unit in
Direct Port Access mode is mapped in Memory space, thus this bit must be zero.
192
April 2004
Developer’s Manual