EW31244SL7QV Datasheet, PDF (33/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
Note: The SDI, SDO and SCLK pins have multiple functions an may require additional functionality as
presented in Table 9. WP# is not documented here. Refer to the vendors’ datasheet.
Table 9.
Serial EEPROM Interface Pins
Name
SDI
SDO
SCLK
SCS#
Description
INPUT - LVTTL with Pull Up: Connects to the serial data output (SO) of the Serial
EEPROM. Data is shifted out of the EEPROM on the falling edge of SCLK. Customers are
recommended to add pads for both a pull-up and a pull-down resistor for possible use in
the future.
OUTPUT - LVTTL: Connects to the serial data input (SI) of the Serial EEPROM. Data is
latched into the Serial EEPROM on the rising edge of SCLK. This is also the activity output
for Channel 3 when all four LEDs are activated (active LOW).
OUTPUT - LVTTL: Connects to the clock input (SCK) of the Serial EEPROM. This is also
the activity LED output for Channel 2 when all four LEDs are activated (active LOW).
OUTPUT - LVTTL with Pull Up: Connects to the chip select input (CS#) of the Serial
EEPROM.
The GD31244 is a Master SPI device which outputs three signals (SCS#, SCLK and SDO) and
inputs one signal (SDI). Only one external device is supported. The SCLK is derived from the
PCI/PCI-X bus CLK signal as presented in Table 10. The GD31244 behaves as if the SPI modes
are CPOL=0 and CPHA=0.
Table 10.
SCLK Frequency
PCI-X Speed
PCI 33 MHz
PCI-X 66 MHz
PCI-X 100 MHz
PCI-X 133 MHz
SCLK
8.25 MHz
16.5 MHz
12.5 MHz
16.625 MHz
Period
121 nsec
60.6 nsec
80 nsec
60.2 nsec
Divider
4
4
8
8
The Serial EEPROM implements the nine commands presented in Table 11. These commands are
supported through the GD31244, either through the PCI Configuration space (offsets 90h and 94h)
or the memory interface.
Table 11.
Serial EEPROM Commands
Command Name
WRSR
PROGRAM
READ
WRDI
RDSR
WREN
RDID
SECTOR ERASE
CHIP ERASE
Op_Code
01h - 0000 0001
02h - 0000 0010
03h - 0000 0011
04h - 0000 0100
05h - 0000 0101
06h - 0000 0110
15h - 0001 0101
52h - 0101 0010
62h - 0110 0010
Access
PCI Config
Memory
Memory
PCI Config
PCI Config
PCI Config
PCI Config
PCI Config
PCI Config
Operation
Write Status Register
Program Data into Memory Array
Read Data from Memory Array
Reset Write Enable Latch
Read Status Register
Set Write Enable Latch
Read Manufacturer and Product ID
Erase One Sector in Memory Array
Erase the entire Memory Array
Developer’s Manual
April 2004
33