EW31244SL7QV Datasheet, PDF (58/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.3.2 Data Synchronization
PCI IDE
Table 21.
For READ DMA transactions, data coming from the SATA device is written by the serial engine
into the FIFO. The DMA then reads the data from the FIFO and writes it into memory. The DMA
and the serial engine operate independently. Therefore, data may remain in the FIFO well after the
SATA device has indicated, through a Device-to-Host Register FIS, that it has completed the
READ DMA transaction. For example, the DMA may be in the middle of flushing the FIFO. The
Device-to-Host FIS contains an interrupt bit that is used to generate an interrupt. However, to
ensure that all the data is transferred into memory, an interrupt is not generated until the FIFO has
been emptied. This means that when a Register Device-to-Host FIS is received with the “I” bit set,
and only after the FIFO has been emptied, that the SATA port sets the Interrupt Status Bit (bit 2) in
the DMA Status Register and then generates an interrupt. Table 21 describes the interrupt status bit
and the DMA active bit states after a DMA transfer has been initiated. Refer to Section 107, “SU
IDE Channel 0 DMA Status Register - SUICDSR0” on page 179 and Section 110, “SU IDE
Channel 1 DMA Status Register - SUICDSR1” on page 182.
Interrupt /Activity Status Combinations
Bit 2
(Interrupt Status Bit)
0₂
1₂
1₂
0₂
Bit 0
(Active Bit)
1₂
0₂
1₂
0₂
Description
DMA transfer is in progress. No interrupt has been generated by
the device.
Device generated an interrupt and the descriptor table has been
exhausted. For example, the last descriptor has been processed.
This is a normal completion where the size of the physical
memory regions is equal to the device transfer size.
Device generated an interrupt. The DMA controller has not
reached the end of the descriptor table. This is a valid completion
case when the size of the physical memory regions is larger than
the device transfer size.
Error condition. When the DMA controller Error bit is 1, the DMA
controller encountered a problem transferring data to/from
memory. Specifics of the error have to be determined using
bus-specific information. When the Error bit is 0, the descriptor
table specified a smaller transfer size than the programmed
transfer size on the device.
Note:
As described in Table 21, for device read transactions the user may program the size of the physical
regions to be larger than the device transfer size. However, during device write transactions the
user must program the physical regions to be equal to the device transfer size. The GD31244
controller uses the DMA end-of-transfer status to complete the device write transaction.
58
April 2004
Developer’s Manual