EW31244SL7QV Datasheet, PDF (71/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.2.3 Control Block Registers
Figure 26.
The Control Block Registers provide control and status of the device. Figure 26 shows the Control
Block Register mapping. Refer to Section , “The SATA Unit may be set up during system reset to
execute in one of the following modes. Each mode provides a different programming interface. The
DPA_MODE# external strap signal is sampled during the rising edge of PCI reset, to determine the
operation mode.” on page 62 for further details on the mapping when in the Direct Port Access mode
(DPA) of the registers for SATA Port 0.
Control Block Registers for SATA Port 0
31
Reserved
Reserved
Device Control/Alternate Status Registers
Reserved
0
Offset
220H
224H
228H
22CH
5.2.4 DMA Controller Registers
Figure 27.
The DMA Controller Registers provide control and status for the DMA Controller. Several ATA
commands use the DMA Controller to transfer data between device and memory. Figure 27 shows
the DMA Controller register mapping when in the Direct Port Access mode (DPA) for SATA
Port 0. Refer to Section , “The SATA Unit may be set up during system reset to execute in one of
the following modes. Each mode provides a different programming interface. The DPA_MODE#
external strap signal is sampled during the rising edge of PCI reset, to determine the operation
mode.” on page 62 for further details on the mapping of the registers.
DMA Controller Registers for SATA Port 0
31
DMA Control Register
DMA Upper Descriptor Table Pointer
DMA Upper Data Buffer Pointer
Reserved
DMA Command/Status Registers
DMA Descriptor Table Pointer
0 Offset
260H
264H
268H
26CH - 26FH
270H
274H
Developer’s Manual
April 2004
71