EW31244SL7QV Datasheet, PDF (164/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.54 SU MSI Message Upper Address Register -
SUMSI_Message_Upper_Address
Table 92.
The Message Upper Address register is set during system initialization when system software
wishes to place the MSI address location above the 4 G address boundary. When this register is set
to a non-zero value, the GD31244 controller will generate a dual address cycle for the MSI write
command and will use the contents of this register as the upper 32-bits of that address.
SU MSI Message Upper Address Register - SUMSI_Message_Upper_Address
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI Configuration Offset
F8H - FBH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
Default
Description
00000000H Message Address - Upper Message Address. This value is set by system software.
164
April 2004
Developer’s Manual