EW31244SL7QV Datasheet, PDF (234/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.10 SU PCI DPA Host BIST Data High Register - SUPDHBDHR
Table 144.
The SU PCI DPA Host BIST Data High Register is the second 32-bit parameter of the SATA Bist
Activate Host-to-Device FIS. Refer to the Serial ATA Specification.
SU PCI DPA Host BIST Data High Register - SUPDHBDHR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 054H,
DPA Mode Offset
Port 0 = 354H, Port 1 = 554H
Port 2 = 754H, Port 3 = 954H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
Default
Description
31:00 0000_0000H This register contains the data transmitted as BIST FIS DWORD 2.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
234
April 2004
Developer’s Manual