EW31244SL7QV Datasheet, PDF (120/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.12 SU Base Address Register 1 - SUBAR1
Table 50.
The SU Base Address Register 1 (SUBAR1) defines the base I/O address of the Control Block
Registers for Channel 0.
SU Base Address Register 1 - SUBAR1
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv ro
PCI Configuration Address Offset
14H - 17H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
31:00
Default
PCI IDE Description
0000_03F5H
Base Address 1 - PCI IDE Mode: These bits define the base address of the Control Block Registers in
PCI I/O space for channel 0.
DPA Mode
0000_0000H Base Address 1 - DPA Mode Upper 32 bits for BAR0
120
April 2004
Developer’s Manual