EW31244SL7QV Datasheet, PDF (155/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 83. SU PCI-X Status Register - SUPCIXSR (Sheet 2 of 2)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rc ro ro ro ro ro ro ro ro ro rc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI Configuration Offset
E4H-E7H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
The GD31244 controller may be configured to identify the add-in card to the system as 64-bit or 32-bit
wide through a user-configurable strap (32BITPCI#). This strap will by default identify the GD31244
16
32BITPCI# ^{controller subsystem as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.}
0 = The bus is 32 bits wide.
1 = The bus is 64 bits wide.
Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
segment for the device containing this function. The function uses this number as part of its Requester
ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
by a Configuration Write transaction, the function must update this register with the contents of AD[7:0]
of the attribute phase of the Configuration Write, regardless of which register in the function is
15:8
FFH
addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
the following are true:
1. The transaction uses a Configuration Write command.
2. IDSEL is asserted during the address phase.
3. AD[1:0] are 00b (Type 0 configuration transaction).
4. AD[10:08] of the configuration address contain the appropriate function number.
Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
containing this function, i.e., the number in the Device Number field (AD[15:11]) of the address of a Type
0 configuration transaction that is assigned to the device containing this function by the connection of
the system hardware. The system must assign a device number other than 00h (00h is reserved for the
source bridge). The function uses this number as part of its Requester ID and Completer ID. Each time
the function is addressed by a Configuration Write transaction, the device must update this register with
7:3
1FH
the contents of AD[15:11] of the address phase of the Configuration Write, regardless of which register
in the function is addressed by the transaction. The function is addressed by a Configuration Write
transaction when all of the following are true:
1. The transaction uses a Configuration Write command.
2. IDSEL is asserted during the address phase.
3. AD[1:0] are 00b (Type 0 configuration transaction).
4. AD[10:08] of the configuration address contain the appropriate function number.
Function Number - This register is read for diagnostic purposes only. It indicates the number of this
2:0
000₂
function; i.e., the number in the Function Number field (AD[10:08]) of the address of a Type 0
configuration transaction to which this function responds. The function uses this number as part of its
Requester ID and Completer ID.
Developer’s Manual
April 2004
155