EW31244SL7QV Datasheet, PDF (148/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.39 SU Master Deferred/Split Sequence Pending Register - SUMDSPR
Table 77.
When a split completion error message is received (SCM bit = 1 and SCE bit = 1), the message
value is written to this register. Bit 29 of the PCI-X Status Register is set when a split completion
error message is received.
SU Master Split Completion Message Received with Error Message Register -
SUMSCMREMR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc
PCI Configuration Address Offset
D0-D3H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
31:00
Default
0000_0000H Master deferred/split sequence pending.
Description
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
148
April 2004
Developer’s Manual