EW31244SL7QV Datasheet, PDF (85/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.2.1.2
Split Response Termination
As an initiator, the GD31244 controller may encounter this error condition in PCI-X mode when
the target signals a Split Response Termination.
Parity errors occurring during Split Response Terminations of Read Requests by the GD31244
controller are recorded, PERR# is asserted (when enabled) and SERR# is asserted (when
enabled). Specifically, the following actions with the given constraints are taken by the GD31244
controller:
• PERR# is asserted three clock cycles following the Split Response Termination in which the
parity error is detected on the bus. This is only done when the Parity Error Response bit in the
SUCMD is set. When the GD31244 controller asserts PERR#, additional actions will be
taken:
— The Master Parity Error bit in the SUSR is set.
— When the SERR# Enable bit in the SUCMD is set, and the Data Parity Error Recover
Enable bit in the SUPCIXCMD register is clear, assert SERR#, otherwise no action.
When the GD31244 controller asserts SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• The Detected Parity Error bit in the SUSR is set.
• Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
Developer’s Manual
April 2004
85