EW31244SL7QV Datasheet, PDF (9/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Figures
1 Intel^® 31244 PCI-X to Serial ATA Controller Block Diagram ...................................................... 21
2 Serial ATA Unit Block Diagram................................................................................................... 26
3 Common LED and Serial EEPROM Options ..............................................................................30
4 Serial EEPROM Interface ........................................................................................................... 32
5 Write Status Register (WRSR) Operation................................................................................... 34
6 Write Memory (PROGRAM) Operation, 4 Byte .......................................................................... 35
7 Read Memory (READ) Operation, 4 Byte ................................................................................... 36
8 Write Disable (WRDI) Operation.................................................................................................37
9 Read Status Register (RDSR) Operation ................................................................................... 38
10 Write Enable (WREN) Operation ................................................................................................ 39
11 Sector Erase (SECT_ERASE) Operation ................................................................................... 40
12 Chip Erase (CHIP_ERASE) Operation ....................................................................................... 41
13 Read ID Register (RDID) Operation ........................................................................................... 42
14 SATA Protocol Layers ................................................................................................................ 49
15 Analog Front End (AFE) Cabling and OOB Signals ................................................................... 50
16 OOB Signals Timings ................................................................................................................. 50
17 COMRESET Sequence .............................................................................................................. 51
18 COMINIT Sequence ................................................................................................................... 52
19 SATA Port Block Diagram .......................................................................................................... 53
20 DMA Descriptor Table ................................................................................................................ 56
21 DMA Arbitration .......................................................................................................................... 60
22 SATA Unit Register Mapping in Native-PCI Mode...................................................................... 68
23 SATA Unit Register Mapping in Direct Port Access Mode ......................................................... 69
24 Common Serial ATA Port Registers ........................................................................................... 70
25 Command Block Registers for SATA Port 0 ............................................................................... 70
26 Control Block Registers for SATA Port 0 .................................................................................... 71
27 DMA Controller Registers for SATA Port 0 ................................................................................. 71
28 Far-End Retimed Loopback Setup ............................................................................................. 79
29 Far-End Analog Loopback Setup................................................................................................ 80
30 Near-End Analog Loopback Setup ............................................................................................. 80
31 SATA Unit Interrupt Generation Block Diagram .......................................................................101
32 SU in PCI IDE Mode Interface Configuration Header Format ..................................................103
33 SATA Unit Interface Extended Configuration Header Format (PCI-X Capability) .................... 104
34 SU in PCI IDE Mode Interface Extended Configuration Header
Format (Power Management)................................................................................................... 104
35 SU in PCI IDE Mode Interface Extended Configuration Header Format (MSI Capability)........ 105
Developer’s Manual
April 2004
9