EW31244SL7QV Datasheet, PDF (96/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 33.
31244 Controller Error Reporting Summary - PCI Interface (Sheet 2 of 3)
Error Condition^a
(Bus Mode^b)
Inbound Read Request
(Immediate Data Transfer)
Parity Error (Both)
Inbound Write Request
Parity Error (Both)
(Both)
Split Completion Message
Parity Error (PCI-X)
(PCI-X)
(PCI-X)
(PCI-X and SCE^e)
(PCI-X)
Outbound Read Request
Master-Abort (Both)
(Both)
(PCI-X and SCE)
Outbound Write Request
Master-Abort (Both)
(Both)
(MSI)
Inbound Read Request
Target-Abort (Both)
(Both)
Inbound Write Request
Target-Abort (Both)
(Both)
Outbound Read Request
Target-Abort (Both)
(Both)
(PCI-X and SCE)
Outbound Write Request
Target-Abort (Both)
(Both)
Bits Set in
SU Status Register
(SUSR^c)
or
SU PCI-X Status Register
(SUPCIXSR^d)
PCI Bus Error Response
(i.e., signal Target-Abort, signal
Master-Abort etc.)
Signal PERR#.
Detected Parity Error - bit 15 of
SUSR
Signal PERR# and SERR#.
Master Parity Error - bit 8 of SUSR
SERR# Asserted - bit 14 of SUSR
Received Split Completion Error
Message - bit 29 SUPCIXSR
Detected Parity Error - bit 15 of
SUSR
None
Master Abort - bit 13 of SUSR
Received Split Completion Error
Message - bit 29 of SUPCIXSR
Signal SERR# (MSI)
Master Abort - bit 13 of SUSR
SERR# Asserted - bit 14 of SUSR
Target Abort (target) - bit 11 of
SUSR
Target Abort (target) - bit 11 of
SUSR
Target Abort (master) - bit 12 of
SUSR
Received Split Completion Error
Message - bit 29 of SUPCIXSR
Signal SERR# (MSI)
Target Abort (master) - bit 12 of
SUSR
PCI IDE Mode
SU IDE Channel 0 DMA
Status Register (SUICDSR0)
or
SU IDE Channel 1 DMA
Status Register (SUICDSR1)
DMA Action
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
DPA Mode
SU PCI DMA Status Register
(SUPDDSR)
DMA Action
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
96
April 2004
Developer’s Manual