EW31244SL7QV Datasheet, PDF (48/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
Functional Blocks
4
4.1
Serial ATA
This section describes the Serial ATA (SATA) unit, including the operation modes and setup.
Throughout this section, this unit is referred to as the SATA Unit or SU. The SATA Unit on 31244
supports four independent SATA ports, but may also be set up to emulate IDE master/slave.
With Parallel ATA (PATA), the controller and the device communicate using a 40-pin ribbon cable.
The controller and device are connected through a parallel bus, which provides address, controls,
and data signals. There are two register blocks on an ATA device:
Command Block Registers:The command block registers are used for normal data transfer requests.
Control Block Registers: The control block registers are used for device control such as software
reset, and bist.
For example, the command block registers are used to issue commands to the device. The parallel
interface also provides a DMA interface. Data may be exchanged between the controller and the
device using either DMA or Programmed I/O (PIO). Refer to the AT Attachment with Packet
Interface-6 (ATA/ATAPI-6) Specification.
SATA maintains the same programming interface. For example, the application still accesses the
device with the same set of registers (Command Block Registers and Control Block Registers).
Since the link between the controller and device is now serial, the device registers are now
manipulated indirectly, requiring that the controller maintains a copy of all the device registers
called the Shadow Register Block (SRB).
The serial bus defines a simple protocol for exchanging messages between the controller and the
device. The serial protocol is transparent to the programmer. For example, the programmer does
not have to be cognizant of how the serial protocol transmit and receive data. Refer to the Serial
ATA Specification.
Information is exchanged between the controller and device over the serial bus using Frame
Information Structures (FISs). The Serial ATA protocol defines a set of FIS:
• Register: Bidirectional
• DMA Activate: Device-to-Host
• DMA Setup: Bidirectional
• BIST Activate: Bidirectional
• Set Device Bits: Device-to-Host
• PIO Setup: Device-to-Host
• Data: Bidirectional
48
April 2004
Developer’s Manual