EW31244SL7QV Datasheet, PDF (142/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.34 SU Interrupt Mask Register SUIMR
Table 72.
This register masks interrupts pending in the Interrupt Pending register. Each bit in the Interrupt
Mask register corresponds to a bit in the Interrupt Pending register. Writing a one to a bit in this
register enables the interrupt source bit. These registers located in configuration space in PCI IDE
mode and in the common space in DPA mode. These registers are located in configuration space
for PCI IDE mode and in the memory space for DPA mode.
SU Interrupt Mask Register - SUIMR
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
31:24
23:16
15:8
7
6
5
4
3
2
1
0
31:00
PCI Configuration Address Offset
AC-AFH PCI IDE
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0
0
0
0
0
0
0
0
0
0
0
0000_0000
PCI IDE Description
Port 4 Interrupt Mask. Same as bits 7:0 corresponding to Port 4
Port 3 Interrupt Mask. Same as bits 7:0 corresponding to Port 3
Port 2 Interrupt Masks. Same as bits 7:0 corresponding to Port 3
Port 1 Interrupt Mask - when high enables Port 1 CRC Interrupts. When low Port 1 CRC Interrupts
are disabled.
When high enables Port 1 CRC Error to generate and interrupt. When low this interrupt source is re
disabled.
When high enables Port 1 Data Integrity Error to generate and interrupt. When low this interrupt
source is disabled.
When high enables Port 1 Unrecognized FIS Reception Error to generate and interrupt. When low
this interrupt source is disabled
When high enables Port 1 RERR Received Error to generate and interrupt. When low this interrupt
source is disabled
When high enables Port 1 FIFO Error to generate and interrupt. When low this interrupt source is
disabled
When high enables Port 1 Going Ready to generate and interrupt. When low this interrupt source is
disabled.
When high enables Port 1 Going Ready to generate and interrupt. When low this interrupt source is
disabled.
PCI DPA Mode Description
Reserved
142
April 2004
Developer’s Manual