EW31244SL7QV Datasheet, PDF (119/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.11 SU Base Address Register 0 - SUBAR0
Table 49.
The SU Base Address Register 0 (SUBAR0) defines the base I/O address of the Command Block
Registers for Channel 0.
SU Base Address Register 0 - SUBAR0
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv ro
PCI Configuration Address Offset
10H - 13H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
31:00
Default
PCI IDE Description
0000_01F1H
Base Address 0 - These bits define the base address of the Command Block Registers in PCI I/O space
for channel 0.
DPA Mode Description
0000_0004H Base Address 0 - 4K of memory for all port registers. Lower 32 bit address.
Developer’s Manual
April 2004
119