EW31244SL7QV Datasheet, PDF (136/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.28 SPI Status Register - SPISTATR
Serial Peripheral Interface (SPI) Status Register definition of this 8 bit register is described in
Table 66. Writes to the serial device must be performed by a special device driver that polls the SPI
Status Register to determine when the write is done. When HIGH indicates that the last command
has been transferred to the serial prom successfully. A LOW indicates that the device is not ready.
Table 66. SPI Status Register - SPISTATR
PCI
Attributes
15
12
8
rv rv rv rv rv rv rv rw
Bit
23:17
16
Default
00h
0b
PCI Configuration Address Offset
92
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Reserved.
Command done. When HIGH indicates that the last command has been communicated to the
serial device. It does not mean the device is ready. The RDSR command must be issued to
determine this.
136
April 2004
Developer’s Manual