EW31244SL7QV Datasheet, PDF (65/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.5.3
First Party DMA (FPDMA)
Serial ATA II Native Command Queuing has a mechanism such that the drive can select the DMA
context for a subsequent data transfer without host software intervention using the GD31244. This
mechanism is called First Party DMA. The drive selects the DMA context by sending a DMA
Setup FIS to the host controller specifying the tag of the command that the data transfer is for. The
host controller will load the scatter/gather table pointer for that command (based on the tag value)
into the DMA engine. Then the DMA transfer may proceed.
The Serial ATA II Native Queuing definition utilizes the reserved 32-bit field in the Set Device Bits
FIS to convey the pending status for each of up to 32 outstanding commands. The BSY bit in the
Status register conveys only the device’s readiness to receive another command, and does not
convey the completion status of queued commands. The 32 reserved bits in the Set Device Bits FIS
are handled as a 32-element array of active command bits (referred to as ACT bits), one for each
possible outstanding command, and the array is bit significant such that bit “n” in the array
corresponds to the pending status of the command with tag “n.”
Data returned by the device (or transferred to the device) for queued commands use the First Party
DMA mechanism to cause the host controller to select the appropriate destination/source memory
buffer for the transfer. The memory handle used for the buffer selection is the same as the tag that is
associated with the command. For traditional desktop host controllers, the handle may be used to
index into a vector of pointers to pre-constructed scatter/gather lists (often referred to as physical
region descriptor tables or simply PRD tables) in order to establish the proper context in the host’s
DMA engine.
Status is returned by updating the 32-element bit array in the Set Device Bits FIS for successful
completions. For failed commands, the device halts processing commands allowing host software
or controller firmware to intervene and resolve the source of the failure before processing is again
explicitly restarted. For more information on native command queueing, see Serial ATA II:
Extensions to Serial ATA 1.0
Developer’s Manual
April 2004
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