EW31244SL7QV Datasheet, PDF (83/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6
5.6.1
PCI Bus Error Conditions
This section describes error handling that occurs on the PCI bus.
PCI error conditions cause state machines to exit normal operation and return to idle states. In
addition, status bits are set to inform error handling code of exact cause of error condition. Error
conditions and status may be found in the SUSR. PCI errors are reported by setting the bit(s) in the
SU Status Register, which correspond to the error condition (master abort, target abort, etc.)
PCI bus error conditions and the action taken on the bus are defined within the PCI Local Bus
Specification, Revision 2.2, and the PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a. The GD31244 controller adheres to the error conditions defined within the PCI
specification for both requester and target operation.
Address and Attribute Parity Errors on the PCI Interface
The GD31244 controller must detect and report address and attribute (PCI-X mode only) parity
errors for transactions on the PCI bus. When an address or attribute parity error occurs on the PCI
interface of the GD31244 controller, the following actions based on the constraints specified:
• In either Conventional mode or PCI-X mode, when the Parity Error Response bit in the
SUCMD is set, the GD31244 controller will target abort the following transactions:
Configuration Read, Configuration Write, I/O Read, I/O Write, and Memory Read. When the
Parity Error Response bit is clear, the transaction will proceed normally. Note that Memory
Write and Outbound Split Completion will complete normally as when there was no parity
errors. For transactions that terminate with a target abort, the following action is taken by the
GD31244 controller:
— Set the Target Abort (target) bit (bit 11) in the SUSR.
• Assert SERR# when the SERR# Enable bit and the Parity Error Response bit in the SUCMD
are set. When the GD31244 controller asserts SERR#, additional action is taken:
— Set the SERR# Asserted bit in the SUSR.
• Set the Detected Parity Error bit in the SUSR.
Developer’s Manual
April 2004
83