EW31244SL7QV Datasheet, PDF (90/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.3.2
5.6.3.2.1
5.6.3.2.2
Master-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as a Target
Unsupported PCI Commands
When the GD31244 controller encounters a PCI or PCI-X command on an inbound transaction that
is not supported, it will signal a master abort by not asserting DEVSEL#. Refer to Table 3 on
page 23 and Table 4 on page 24.
PCI IDE Control Block Registers
In PCI IDE mode, the Control Block registers are located in the I/O space, and the smallest amount
of I/O space that a Base Address Register may request is four bytes. The Control Block is accessed
using Base Address Registers 1 and 3 for the primary and secondary channels respectively. In this
four byte allocation for the Control Block, the byte at offset 02H is where the Alternate
Status/Device Control registers are located. The GD31244 controller will master abort access made
to the bytes at offsets (00H, 01H, and 03H) by not asserting DEVSEL#.
90
April 2004
Developer’s Manual