EW31244SL7QV Datasheet, PDF (229/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 140. SU PCI DPA BIST FIS Control and Status Register - SUPDBFCSR (Sheet 2 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rv rv rw rw rw rv rv rv rv rv rv rw ro ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 044H,
Bit
Default
20
0₂
19
0₂
18
0₂
17
0₂
16
0₂
15
0₂
14
0₂
13
0₂
12
0₂
11
0₂
10
0₂
09
0₂
08
0₂
07
0₂
06
0₂
05
0₂
04
0₂
03
0₂
02
0₂
01
0₂
DPA Mode Offset
Port 0 = 344H, Port 1 = 544H
Port 2 = 744H, Port 3 = 944H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Enable near end loop back confirm 1=loopback, 0=normal.
OOB Bypass. Setting this bit to a “1” will cause OOB processing to be bypassed.
Setting this bit to a “1” will force JTAG disable.
Setting this bit to a “1” will bypass transmit and receive scramblers, as well as no CONT primitive
insertion.
Setting this bit high will cause the PHY to transmit a continuous stream of K28.5s. This is an independent
bit that simply sends a stream of K28.5s over the serial bus. Does not require any other setup.
BIST Activate FIS has been received, and this device is in BIST mode.
BIST Activate FIS received with transmit-only bit set. When set, this bit indicates that the far-end device
is requesting a transmit-only setup, and to transmit the DWORDs in SU PCI DPA Device BIST Data Low
Register - SUPDDBDLR and SU PCI DPA Device BIST Data High Register - SUPDDBDHR. These are
the DWORDs received as part of the BIST Activate FIS.
BIST Activate FIS received with align bypass bit set. This bit must be qualified when bit 14 is set.
BIST Activate FIS received with scrambling bypass bit set. This bit must be qualified when bit 14 is set.
BIST Activate FIS received with retimed bit set. When set, this bit indicates that the far-end device is
requesting a retimed loopback setup path.
BIST Activate FIS received with primitive bit set. This bit must be qualified when bit 14 is set.
BIST Activate FIS received with AFE loopback bit set. When set, this bit indicates that the far-end device
is requesting an AFE Analog loopback each setup.
Setting this bit high will cause the PHY to transmit a continuous stream of K28.5s. This is an
independent bit that sends a stream of K28.7s over the serial bus. Does not require any other setup.
Send BIST Activate FIS. This bit is used to initiate the transfer of a BIST Activate FIS to the far-end
device. Bits [6:1] must be setup accordingly before setting this bit.
Send BIST Activate FIS with transmit-only bit set. This bit is used to command the far-end device to
place itself in a transmit-only mode, and to transmit data patterns indicated in the BIST Activate FIS
(Data DWORDs) it received from the sender. Bits 5, 4 and 2 may optionally be used when requesting
this mode.
Send BIST Activate FIS with align bypass bit set. This bit may be used in conjunction with bit 6.
Send BIST Activate FIS with scrambling bypass bit set. This bit may be used in conjunction with bit 6.
Send BIST Activate FIS with retimed bit set. This bit is used to command the far-end device to setup a
retimed loopback path.
Send BIST Activate FIS with primitive bit set. This bit may be used in conjunction with bit 6.
Send BIST Activate FIS with AFE loopback bit set. This bit is used to command the far-end device to
setup an AFE Analog loopback path.
Developer’s Manual
April 2004
229