EW31244SL7QV Datasheet, PDF (24/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2.3.1
Table 4.
PCI Commands Supported in DPA Mode
In DPA Mode, the SATA Unit registers are mapped in memory space using one base address
register. Each port supports its own DMA and each SATA port device may be independently
controlled. Table 4 shows the PCI and PCI-X commands supported for both inbound and outbound
transactions when in DPA Mode.
PCI Commands Supported in DPA Mode
PCI Command
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PCI Command
Type
PCI-X Command
Type
Claimed on
Inbound Transac-
tions on PCI Bus?
Generated by
Outbound Trans-
actions on PCI
Bus?
Interrupt
Interrupt
No
No
Acknowledge
Acknowledge
Special Cycle
Special Cycle
No
No
I/O Read
I/O Read
No
No
I/O Write
I/O Write
No
No
Reserved
Reserved
No
No
Reserved
Reserved
No
No
Memory Read
Memory Read
DWORD
Yes
Memory Write
Memory Write
Yes
Reserved
Alias to Memory
Read Block
PCI-X = Yes
PCI = No
Reserved
Alias to Memory
Write Block
PCI-X = Yes
PCI = No
ConfigurationRead ^{ConfigurationRead Yes}
Configuration Write Configuration Write Yes
Memory Read
Multiple
Split Completion
Yes
Dual Address Cycle Dual Address Cycle Yes
Memory Read Line
Memory Read
Block
Yes
Memory Write
Invalidate
Memory Write Block Yes
Yes
Yes
No
No
No
No
PCI-X = No
PCI = Yes
Yes
Yes
Yes
For inbound transactions in conventional PCI, Memory Read transactions are
disconnected-with-data on the first data phase. For example, when a Memory Read transaction is
requesting more than one DWORD, the transaction is disconnected on the first DWORD. The
GD31244 controller aliases Memory Read Line (MRL) and Memory Read Multiple (MRM) to
Memory Read. Memory Write (MW) is also disconnected-with-data on the first data phase. For
example, only the first DWORD is claimed and then the transaction is disconnected. The GD31244
controller aliases Memory Write and Invalidate (MWI) to Memory Write. In PCI-X mode, Memory
Read Block and Memory Write Block are single-phase-disconnected.
24
April 2004
Developer’s Manual