EW31244SL7QV Datasheet, PDF (115/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.7
Table 45.
SU Cacheline Size Register - SUCLSR
Cacheline Size Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2. This
register is programmed with the system cacheline size in DWORDs (32-bit words). The GD31244
controller may burst up to a maximum of 512 bytes per request. The Cacheline Size register defines
burst boundaries for bus master/DMA transactions generated by the GD31244 controller. For
example, when a DMA transaction starts on a non-aligned cacheline address, the DMA controller
starts the transaction by bursting from that unaligned address until the next cacheline boundary is
reached. Subsequent DMA transactions then starts on cacheline boundaries and burst up to a
maximum of 512 bytes. A value of zero means that burst transactions takes place on unaligned
boundaries, transferring up to 512 bytes.
SU Cacheline Size Register - SUCLSR
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
Bit
07:00
PCI Configuration Address Offset
0CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Default
00H
Description
SU Cacheline Size - CLS specifies the system cacheline size in DWORDs.
CLS Burst Length
00 80h, 40h, 20h, 10h, 08h
08 80h, 40h, 20h, 10h, 08h
10 80h, 40h, 20h,10h
20 80h, 40h, 20h
40 80h, 40h
80 80h
other 80h, 40h, 20h, 10h, 08h
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Developer’s Manual
April 2004
115