EW31244SL7QV Datasheet, PDF (91/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.4
5.6.4.1
Target Aborts on the PCI Interface
As an initiator on the PCI bus, the GD31244 controller may encounter target abort conditions
during:
• Outbound Read Request
• Outbound Write Request
• Outbound Read Completion
As a target, the GD31244 controller PCI interface is capable of signaling a target abort case during:
• Configuration Read
• Configuration Write
• I/O Read
• I/O Write
• Memory Read
Target Aborts for Outbound Read Request or Outbound
Write Request
This error may be encountered by the GD31244 controller in both the Conventional and PCI-X
modes. For an Outbound transaction, there are two ways in which a Target-Abort may be signaled
to the GD31244 controller:
1. In the Conventional or PCI-X modes, a target abort is signaled when the target of the
transaction simultaneously deasserts DEVSEL#, deasserts TRDY#, and asserts STOP#.
2. In PCI-X mode, the GD31244 controller may initiate a split request (read request) to the
target-side interface of a PCI-to-PCI bridge. When the PCI-to-PCI bridge detects a Target Abort
on its initiating interface for that Split Request, target abort is signaled to GD31244 controller
through a Target-Abort Split Completion Error Message (class = 1h - bridge error and index =
01h - Target Abort). The following actions with the given constraints are performed by the
GD31244 controller when a target abort is detected by the PCI initiator interface or the PCI target
interface receives a Target-Abort Split Completion error message:
• Set the Target Abort (master) bit (bit 12) in the SUSR.
• When the transaction is an MSI outbound write and the SERR# Enable bit in the SUCMD is
set, assert SERR#; otherwise, no action is taken. When the GD31244 controller asserts
SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• When operating in the PCI-X mode and the Target-Abort is signaled through a Split
Completion Error Message, the Received Split Completion Error Message bit in the
SUPCIXSR is set.
• Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
Developer’s Manual
April 2004
91