EW31244SL7QV Datasheet, PDF (232/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.8 SU PCI DPA BIST Frames Register - SUPDBFR
Table 142.
The SU PCI DPA BIST Frames Register is a 32-bit register. This register is used during far-end
loopback testing, and is only used for the counting pattern. Refer to bits [31:30] of the SU PCI DPA
BIST FIS Control and Status Register - SUPDBFCSR for pattern selection.
SU PCI DPA BIST Frames Register - SUPDBFR
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI IDE Mode BAR5 Offset
= 04CH,
DPA Mode Offset
Port 0 = 34CH, Port 1 = 54CH
Port 2 = 74CH, Port 3 = 94CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
Default
Description
BIST Frames. This register contains the number of BIST Frames that occurred since the last time the
0000_0000H BIST FIS Control and Status register bit 25 was set. A BIST frame is 65536 DWORDs. Refer to
Section 5.5, “Serial ATA BIST” on page 79 for a description of a BIST Frame.
232
April 2004
Developer’s Manual