EW31244SL7QV Datasheet, PDF (88/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.2.6
Split Completion Messages
As a target, the GD31244 controller may encounter this error when operating in the PCI-X Mode.
Data parity errors occurring during Split Completion Messages claimed by the GD31244 controller
may assert PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error
occurs, the GD31244 controller will accept the data and complete normally. Specifically, the
following actions with the given constraints are taken by the GD31244 controller:
• PERR# is asserted three clocks cycles following the data phase in which the data parity error
is detected on the bus. This is only done when the Parity Error Response bit in the SUCMD is
set. When the GD31244 controller asserts PERR#, additional actions are taken:
— The Master Parity Error bit in the SUSR is set.
— When the SERR# Enable bit in the SUCMD is set, and the Data Parity Error Recover
Enable bit in the SUPCIXCMD register is clear, assert SERR#; otherwise no action is
taken. When the GD31244 controller asserts SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
the Attribute phase, the Received Split Completion Error Message bit in the SUPCIXSR is set.
When the GD31244 controller sets this bit, additional actions are taken:
— The Detected Parity Error bit in the SUSR is set.
— Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
88
April 2004
Developer’s Manual