EW31244SL7QV Datasheet, PDF (239/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.15 SU PCI DPA DMA Setup FIS Control and
Status Register - SUPDDSFCSR
Table 149.
The SU PCI DPA DMA Setup FIS Control and Status Register is a 32-bit register. This register is
used to initiate a DMA Setup FIS. This register also contains the status of a received DMA Setup FIS.
SU PCI DPA DMA Setup FIS Control and Status Register - SUPDDSFCSR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw ro rv rw rw rv rv rw rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv
PCI IDE Mode Offset
= 068H,
Bit
Default
31
30
29
28
27
26
25
24
23
22
21:16
15
14
13
12
11
10
9
8
07:00
0₂
0₂
0₂
0₂
0₂
0₂
0₂
0₂
0₂
0₂
000000₂
0₂
0₂
0₂
0₂
0₂
0₂
0₂
0₂
00H
DPA Mode Offset
Port 0 = 368H, Port 1 = 568H
Port 2 = 768H, Port 3 = 968H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Direction bit. This bit affects first party setup FIS word 0 direction bit.
0 = Receive (receiver to transmitter)
1 = Send (transmitter to receiver)
Interrupt – received first party setup FIS with the I bit set.
Reserved.
Start DMA Setup FIS Bit. Start transmission of DMA setup FIS. A one shot and will always read back a
0.
Enable first party DMA auto processing for command queuing. Enables DMA controller to automatically
process DMA Setup FIS data in order to choose a DMA descriptor table for a queued command.
Reserved.
Reserved.
Abort TSM – Setting this bit will stop the transport/link state machines. This bit is one-shot, and will be
cleared after the TSM goes idle.
The last FIS sent received an RNAK primitive as response.
Reserved.
Reserved.
Reserved
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Developer’s Manual
April 2004
239