EW31244SL7QV Datasheet, PDF (116/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.8
Table 46.
SU Latency Timer Register - SULT
SU Latency Timer Register bit definitions apply to the PCI interface.
SU Latency Timer Register - SULT
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
PCI Configuration Address Offset
0DH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:00
00H
(Conventional
Mode) ^{Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.}
The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
40H
(PCI-X Mode)
116
April 2004
Developer’s Manual