EW31244SL7QV Datasheet, PDF (144/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.36 SU Target Split Completion Message Enable Register SUTSCMER
Table 74.
This register contains any split completion error messages received (SCM bit = 1 and SCE bit = 1).
Bit 29 of the PCI configuration Status Register is set when a split completion error message is
received.
SU Target Split Completion Message Enable Register- SUTSCMER
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI Configuration Address Offset
C4-C7
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
31:0
0
Target read delayed transaction for I/O and non-prefetchable regions discarded. Write 1 to clear.
144
April 2004
Developer’s Manual