EW31244SL7QV Datasheet, PDF (64/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.5.1
4.2.5.2
Race-free Status Return Mechanism
Serial ATA II Native Command Queuing has a race-free status return mechanism that allows status
to be returned on any command at any time. There is no handshake required with the host for the
status return. The drive may issue command completions for multiple commands back-to-back or
even at the same time.
The Serial ATA II Native Queuing definition utilizes the reserved 32-bit field in the Set Device Bits
FIS to convey the pending status for each of up to 32 outstanding commands. The BSY bit in the
Status register conveys only the device’s readiness to receive another command, and does not
convey the completion status of queued commands. The 32 reserved bits in the Set Device Bits FIS
are handled as a 32-element array of active command bits (referred to as ACT bits), one for each
possible outstanding command, and the array is bit significant such that bit “n” in the array
corresponds to the pending status of the command with tag “n.”
The SActive register is used to track completion status of queued commands. This register is part
of the control, status and error superset registers defined in the Serial ATA specification. In
GD31244 this register is known as the Set Device Bits FIS Register SUPDSDBR.
Before host driver software issues a queued command to the device, it sets the bit corresponding to
the tag of the queued command it is about to issue. When the device completes a queued command,
it clears the bit corresponding to the tag of the queued command in the SActive bits in the Set
Device Bits FIS. When the GD31244 receives the Set Device Bits FIS from the device it will
automatically clears the bit corresponding to the tag of the queued command in the Set Device Bits
FIS Register SUPDSDBR (SActive register). Host driver software queries the SActive register to
determine which commands are complete.
This mechanism of the host controller setting bits in the register and the device clearing bits in the
register ensures that no race condition can occur.
These examples describe how the bit field relates to the status of queued commands:
• 1 in bit location 0 signifies that the command with tag 0 is still pending
• 1 in bit location 16 signifies that the command with tag 16 is still pending
• 0 in bit location 16 signifies that the command with tag 16 is complete (if the bit was
previously set)
Interrupt Aggregation
Serial ATA II Native Command Queuing has a maximum of one interrupt per command. In
actuality, the number of interrupts per command is less than one due to a feature called interrupt
aggregation. If the drive completes multiple commands in a short time span, the individual
interrupts for each command may be aggregated into one interrupt by the GD31244. In this case,
the host software driver only sees one interrupt for multiple commands. In a highly queued
workload this is a frequent occurrence since host software interrupt service latency may be long in
comparison to the time between command completions.
64
April 2004
Developer’s Manual