EW31244SL7QV Datasheet, PDF (118/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.10 SU BIST Register - SUBISTR
Table 48.
The SU BIST Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2.
SU BIST Register - SUBISTR
PCI
Attributes
7
4
0
ro rw rv rv rw rw rw rw
Bit
07
06
05:04
03:00
PCI Configuration Address Offset
0FH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0₂
0₂
00₂
0000₂
Description
BIST Capable - This bit always returns a zero, meaning that this unit is not BIST capable.
Start BIST - Writing a one to this bit will invoke BIST. This bit will stay high until BIST is complete.
Reserved
BIST Completion Code.
118
April 2004
Developer’s Manual