EW31244SL7QV Datasheet, PDF (183/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.5.6
Table 111.
SU IDE Channel 1 DMA Descriptor Table
Pointer Register - SUICDDTPR1
This SU IDE Channel 1 DMA Descriptor Table Pointer Register contains the lower 32-bit PCI
address. In PCI IDE mode, the SU IDE Channel 0 DMA Descriptor Table Pointer Register points
to system memory.
SU IDE Channel 1 DMA Descriptor Table Pointer Register - SUICDDTPR1
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv
PCI IDE Mode BAR4 Offset
= 0CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:02
01:00
Default
Description
0000 0000H
PCI Address - is lower PCI address. This register contains the base address of the descriptor table. The
descriptor table must be DWORD aligned and must not cross a 64 Kbyte boundary.
00₂
Reserved.
Developer’s Manual
April 2004
183