EW31244SL7QV Datasheet, PDF (60/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.3.4
Table 22.
DMA Throughput
The PCI bus efficiency is improved, by allowing large data packets to be transferred. The 31244
controller allows up to 512-byte packets per burst transfer on the PCI bus. Table 22 and Table 23
show the PCI-X bus efficiency, based on various packet sizes for read and write transactions
respectively. The tables clearly indicate how, by transferring larger data packets, more bandwidth is
available on the PCI-X bus.
PCI-X Bus Efficiency for Reads
Read Transaction PCI-X Data
Read Overhead
Size (Bytes)
Cycles Cycles (Split Reads)
64
8
11
128
16
11
256
32
11
512
64
11
1024
128
11
Bus
Efficiency
42%
59%
74%
85%
92%
Available Bandwidth (MB/Sec)
66 MHz
222
311
390
435
485
100 MHz
336
472
592
680
736
133 MHz
446
627
787
904
978
Table 23.
Figure 21.
PCI-X Bus Efficiency for Writes
Write Transaction PCI-X Data
Size (Bytes)
Cycles
64
8
128
16
256
32
512
64
1024
128
Write Overhead
Cycles
4
4
4
4
4
Bus
Efficiency
66%
80%
88%
94%
96%
Available Bandwidth (MB/Sec)
66 MHz
348
422
464
496
506
100MHz
528
640
704
752
768
133MHz
702
851
936
1000
1021
In DPA Mode the 31244 controller provides one DMA engine per SATA port. Each SATA port also
supports a 1 Kbyte FIFO. Each SATA port DMA operates independently and may transfer up to
512 bytes in one transfer.
DMA Arbitration
SATA Port 0 DMA
PCI-X
Interface
ARB
SATA Port 1 DMA
SATA Port 2 DMA
SATA Port 3 DMA
A9375-01
To accommodate multiple DMA engines to operate concurrently, the 31244 controller employs an
internal arbiter that controls the SATA ports DMA. The arbiter allows the DMAs to post requests in
a round-robin fashion, thus providing a fair algorithm to the SATA ports.
60
April 2004
Developer’s Manual