EW31244SL7QV Datasheet, PDF (92/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.4.2
5.6.4.2.1
5.6.4.2.2
5.6.4.2.3
Target-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as a Target
Configuration Read and Write
In both Conventional PCI and PCI-X modes, when an address parity error or attribute parity error
(PCI-X Mode only) is detected during a Configuration read or write, the GD31244 controller will
target abort the transaction. The following action is taken when the GD31244 controller signal a
target abort:
• Set the Target Abort (target) bit (bit 11) in the SUSR.
I/O Read and Write
In both Conventional PCI and PCI-X modes, when an address parity error or attribute parity error
(PCI-X Mode only) is detected during a I/O read or write, the GD31244 controller will target abort
the transaction.The following action is taken when the GD31244 controller signal a target abort:
• Set the Target Abort (target) bit (bit 11) in the SUSR.
Memory Read
In both Conventional PCI and PCI-X modes, when an address parity error or attribute parity error
(PCI-X Mode only) is detected during a Memory read, the GD31244 controller will target abort the
transaction. Note that an address or attribute parity error occurring on a Memory write is completed
normally as when no error occurred. The following action is taken when the GD31244 controller
signal a target abort:
• Set the Target Abort (target) bit (bit 11) in the SUSR.
92
April 2004
Developer’s Manual