EW31244SL7QV Datasheet, PDF (143/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.35 SU Transaction Control SUTCR
Table 73.
This register provides primary transaction control. The bits in the register should be set at reset
values only.
SU Transaction Control Register - SUTCR
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
31
30
29
28
27
26
25
24
23
22:20
19:16
15:4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0h
0
000h
0
0
0
0
PCI Configuration Address Offset
C0-C3
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Target read delayed transaction for I/O and non-prefetchable regions discarded. Write 1 to clear.
Target read delayed transaction for all regions discarded. Write 1 to clear.
Target (I/O and memory) read delayed/split at time out/immediately (default time out)
Target (I/O and memory) read delayed/split at time out/immediately (default time out)
Target (I/O and memory) read delayed /split or retry select (if application interface is not ready)
0 = delayed/split transaction
1 = retry transaction (always immediate retry, no AT_REQ to application)
Target (I/O and memory) read target abort enable (if application interface is not ready at the latency
time out)
Target (I/O) write split enable (at time out/immediately; default time out)
Target (I/O) write split enable (if application interface is not ready)
Target (read/write) master abort enable; check at the start of each transaction.
Target subsequent latency time out enable: 0 = 8, 1 to 7.
Target initial latency time-out in PCI mode: 0= 16, 8 to 15
Programmable boundary enable to disconnect/prefetch for target burst read cycles to prefetchable
region in PCI. A value of 1 indicates end of boundary (64KB down to 16 bytes).
Disconnect/prefetch to prefetchable memory regions enable. Prefetchable memory regions are
always disconnected on a region boundary. Non-prefetchable regions for PCI are always
disconnected on the first transfer.
Reserved
Target split write control
0 = blocks all requests except PMW
1 = blocks all requests including PMW until split completion occurs.
cr_lat_timer_disable
Developer’s Manual
April 2004
143