EW31244SL7QV Datasheet, PDF (200/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.8.2 SU PCI DPA Interrupt Mask Register - SUPDIMR
Table 117.
The SU PCI DPA Interrupt Mask Register is a 32-bit register. This register is used to mask
interrupts pending in the SU PCI DPA Interrupt Pending Register. Each bit in the SU PCI DPA
Interrupt Mask Register corresponds to a bit in the SU PCI DPA Interrupt Pending Register. Refer
to Section 5.10.8.1, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
SU PCI DPA Interrupt Mask Register - SUPDIMR (Sheet 1 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
DPA Mode BAR0 Offset
004H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 3 IDE Interrupt Mask Bit.
31
1₂
0 = Masked
1 = Not Masked
SATA Port 3 Signal Detect Interrupt Mask Bit.
30
0₂
0 = Masked
1 = Not Masked
SATA Port 3 Data Integrity Interrupt Mask Bit.
29
0₂
0 = Masked
1 = Not Masked
SATA Port 3 Unrecognized FIS Reception Interrupt Mask Bit.
28
0₂
0 = Masked
1 = Not Masked
SATA Port 3 R_ERR Primitive Received Interrupt Mask Bit.
27
0₂
0 = Masked
1 = Not Masked
SATA Port 3 FIFO Error Interrupt Mask Bit.
26
0₂
0 = Masked
1 = Not Masked
SATA Port 3 PHY Ready Interrupt Mask Bit.
25
0₂
0 = Masked
1 = Not Masked
SATA Port 3 PHY Change State Interrupt Mask Bit.
24
0₂
0 = Masked
1 = Not Masked
SATA Port 2 IDE Interrupt Mask Bit.
23
1₂
0 = Masked
1 = Not Masked
SATA Port 2 Signal Detect Interrupt Mask Bit.
22
0₂
0 = Masked
1 = Not Masked
200
April 2004
Developer’s Manual