EW31244SL7QV Datasheet, PDF (86/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.2.2
5.6.2.2.1
5.6.2.2.2
Outbound Write Request Data Parity Errors
Outbound Writes that are Not MSI (Message Signaled Interrupts)
As an initiator, the GD31244 controller may encounter this error condition when operating in either
the Conventional or PCI-X modes.
Data parity errors occurring during write operations initiated by the GD31244 controller may
record the assertion of PERR# from the target on the PCI Bus. Specifically, the following actions
with the given constraints are taken by the GD31244 controller:
• When PERR# is sampled active and the Parity Error Response bit in the SUCMD is set, set
the Master Parity Error bit in the SUSR. When the Parity Error Response bit in the SUCMD is
clear, no action is taken. When the Master Parity Error bit in the SUSR is set, additional
actions will be taken:
— When the GD31244 controller is operating in the PCI-X mode, the SERR# Enable bit in
the SUCMD is set, and the Data Parity Error Recover Enable bit in the SUPCIXCMD
register is clear, assert SERR#, otherwise no action. When the GD31244 controller asserts
SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
MSI Outbound Writes
As an initiator, the GD31244 controller may encounter this error condition when operating in either
the Conventional or PCI-X modes.
Data parity errors occurring during MSI write operations initiated by the GD31244 controller may
record the assertion of PERR# from the target on the PCI Bus. When an error occurs, the GD31244
controller will complete the transaction normally. Then, the following actions with the given
constraints are taken by the GD31244 controller:
• When PERR# is sampled active and the Parity Error Response bit in the SUCMD is set, set
the Master Parity Error bit in the SUSR. When the Parity Error Response bit in the SUCMD is
clear, no action is taken. When the Master Parity Error bit in the SUSR is set, additional
actions will be taken:
— When the SERR# Enable bit in the SUCMD is set, assert SERR#, otherwise no action.
When the GD31244 controller asserts SERR#, additional actions will be taken:
Set the SERR# Asserted bit in the SUSR.
86
April 2004
Developer’s Manual