EW31244SL7QV Datasheet, PDF (81/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.5.1 Loopback Mode Testing
In the loopback modes (Far-End Retimed or Far-End Analog), the GD31244 controller may be
programmed to generate one of four BIST patterns:
• 00₂ - D2.5s
• 01₂ - D24.3s
• 10₂ - 3(D10.2s) and K28.5
• 11₂ - 16-bit counting pattern
A BIST pattern is selected by programming bits [31:30] of the SU PCI DPA BIST FIS Control and
Status Register - SUPDBFCSR. Programming bits [31:30] with 00₂ will generate a stream of D2.5
data characters. Programming bits [31:30] with 01₂ will generate a stream of D24.3 data characters.
Programming bits [31:30] with 10₂ will generate a stream of three D10.2 data and one K28.5
control characters. Programming bits [31:30] with 11₂ will generate a 16-bit counting pattern. The
counting pattern is a sequence of 65536 DWORDs, repeated indefinitely until the test is concluded.
Each sequence contains DWORDs incremented by one starting with (DWORD = 0000_0000H)
and ends with (DWORD = FFFF_FFFFH). For example, the sequence looks as such: 0000_0000H,
0001_0001H, 0002_0002H, ---------, FFFE_FFFEH, and FFFF_FFFFH. Note that the upper 16-bit
of each DWORD is also incremented in the same manner as the lower 16-bit, and therefore looks
exactly the same as the lower 16-bit.
Before initiating the transfer of a BIST Activate FIS, bits [6:1] of the SU PCI DPA BIST FIS
Control and Status Register - SUPDBFCSR must be set appropriately. For example, to command
the receiver into a Far-End Retimed loopback mode, bit 3 (BIST FIS retimed bit) of the SU PCI
DPA BIST FIS Control and Status Register - SUPDBFCSR must be set. And to command the
receiver into the Far-End Analog loopback mode, bit 1 (BIST FIS AFE loopback bit) must be set.
After the appropriate bit(s) are set in bits [6:1], the BIST Activate FIS may be sent to the receiving
device by setting bit 7.
The GD31244 controller also provides the following registers in order to monitor the BIST tests:
SU PCI DPA BIST Errors Register - SUPDBER and SU PCI DPA BIST Frames Register -
SUPDBFR. The SU PCI DPA BIST Errors Register - SUPDBER is used to keep track of the
number of errors detected. The SU PCI DPA BIST Frames Register - SUPDBFR is used when
BIST pattern (11₂ - 16-bit Counting pattern) is selected. This register keeps track of the number of
BIST frames encountered. A frame is defined as one of the 16-bit counting pattern sequence
described above.
These steps provide an example of how a loopback test may be setup and initiated:
1. Set bit 25, this will clear/reset the BIST Errors and BIST Frames registers.
2. Set bits [31:30] to select one of the BIST patterns.
3. Set bits [29:28], must be set with the same value as bits [31:30] respectively. These bits
indicate the pattern that the checker uses to compare the incoming data stream against.
4. Set bit 1 or bit 3 to select AFE or Retimed loopback respectively.
5. Set bit 24, this bit enables the pattern generator.
6. Set bit 23, this bit enables the pattern checker.
Note: To conclude the loopback test, the far-end device must be reset using a COMRESET/COMINIT
sequence.
Developer’s Manual
April 2004
81