EW31244SL7QV Datasheet, PDF (147/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 76.
SU Transaction Control 2 Register- SUTC2R
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw ro ro ro ro ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
26:24
23:16
15
14
13
12
11
10:9
8
7
6
5
4:0
Default
010b
0000000b
0
0
0
0
0
00
0
0
0
0
0001
PCI Configuration Address Offset
CC-CF
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Master deferred read request outstanding max count. PCI mode only.
Bits 26:24=000b, Max# SAC Cycles=8, Max# DAC Cycles=4
Bits 26:24=001b, Max# SAC Cycles=1, Max# DAC Cycles=0
Bits 26:24=010b, Max# SAC Cycles=2, Max# DAC Cycles=1
Bits 26:24=011b, Max# SAC Cycles=3, Max# DAC Cycles=1
Bits 26:24=100b, Max# SAC Cycles=4, Max# DAC Cycles=2
Bits 26:24=101b, Max# SAC Cycles=5, Max# DAC Cycles=2
Bits 26:24=110b, Max# SAC Cycles=6, Max# DAC Cycles=3
Bits 26:24=111b, Max# SAC Cycles=7, Max# DAC Cycles=3
For the PCI-X maximum outstanding split transactions, refer to crE0[22:20].
Target/master error sequence number.
Target error command indication
0 = delayed/split
1 = others.
Target/master error indication
0 = target
1 = master
Target/master system error. This bit is set whenever ATM_SERR_O is active. Write one to clear.
Target/master data PERR# error status. This bit is set whenever ATM_DATA_PERR_O is active.
Write one to clear.
Target/master address PERR# error status. This bit is set whenever ATM_ADD_PERR_O is active.
Write one to clear.
Reserved.
Target illegal I/O DWORD byte combinations detected. Write one to
clear.
Target illegal I/O DWORD byte detection ENABLE. Allows error to set
SERR if SERR is enabled, also sets bit 8 above.
Reserved
Target I/O delayed split request outstanding maximum count:
0 = CCh[4:0]
1 = 1.
Target delayed/split request outstanding maximum count: 0 = 32, 1 to 31.
Developer’s Manual
April 2004
147