EW31244SL7QV Datasheet, PDF (34/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1
Write Status Register (WRSR) Command
The WRSR command allows the user to control three bits within the EEPROM status register
relating to write protection: WPEN, BP1 and BP0. The EEPROM is divided into four sectors that
may be selectively write protected sectors where the top quarter (1/4), top half (1/2), or all of the
memory sectors may be protected (locked out) from write. The AT25F512 is divided into two
sectors where all of the memory sectors may be protected (locked out) from write. Any of the
locked-out sec-tors will therefore be READ only. The locked-out sector and the corresponding
status register control bits are presented in Table 12.
Table 12. Block Write Protect Bits
Level
Status Bit Registers
BP1
BP0
0
0
0
1 (1/4)
0
1
2 (1/2)
1
0
3 (All)
1
1
AT25F512
Array Addresses
Locked Out
Locked-out Sectors
None
000000 - 00FFFF
None
All sectors (1-2)
AT25F1024
Array Addresses
Locked Out
None
018000 - 01FFFF
010000 - 01FFFF
000000 - 01FFFF
Locked-out Sectors
None
Sector 4
Sector 3, 4
All sectors (1-4)
The three bits, BP0, BP1, and WPEN, are nonvolatile cells that have the same proper-ties and
functions as the regular memory cells (e.g., WREN, t WC, RDSR).
The WRSR command also allows the user to enable or disable the Write Protect (WP) pin through the
use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is
low and the WPEN bit is 1. Hardware write protection is disabled when either the WP pin is high or the
WPEN bit is 0. When the device is hard-ware write protected, writes to the Status Register, including the
Block Protect bits and the WPEN bit, and the locked-out sectors in the memory array are disabled. Write
is only allowed to sectors of the memory which are not locked out. The WRSR command is self-timed
to automatically erase and program BP0, BP1, and WPEN bits. In order to write the status register, the
device must first be write enabled through the WREN command. Then, the command and data for the
three bits are entered. During the internal write cycle, all commands will be ignored except RDSR
commands. The AT25F512/1024 will automatically return to write disable state at the completion of the
WRSR cycle. The WRSR operation is shown in Figure 5.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to 0, as long as the WP
pin is held low.
Figure 5. Write Status Register (WRSR) Operation
SCS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDO
00000001 76543210
WPEN
Reserved- Write as 0
Reserved- Write as 0
Reserved-Write as 0
RDY# - Write as 0
WEN - Write as 0
BP0 - Block Write Protect bit 0
BP1 - Block Write Protect bit 1
SDI
Hi -Z
34
April 2004
Developer’s Manual