EW31244SL7QV Datasheet, PDF (7/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
5.10.7 SU PCI DPA Mode Base Address Registers ....................................................... 192
5.10.7.1 SU PCI DPA Base Address Register 0 - SUPDBAR0 ......................... 192
5.10.7.2 SU PCI DPA Upper Base Address Register 0 - SUPDUBAR0 ............193
5.10.8 SU PCI DPA Mode Common SATA Port Registers.............................................194
5.10.8.1 SU PCI DPA Interrupt Pending Register - SUPDIPR .......................... 194
5.10.8.2 SU PCI DPA Interrupt Mask Register - SUPDIMR .............................. 200
5.10.9 SU PCI DPA Mode Command Block Registers ................................................... 203
5.10.9.1 SU PCI DPA Data Port Register - SUPDDR........................................ 203
5.10.9.2 SU PCI DPA Error Register - SUPDER ............................................... 204
5.10.9.3 SU PCI DPA Features Register - SUPDFR ......................................... 205
5.10.9.4 SU PCI DPA Sector Count Register - SUPDSCR ...............................206
5.10.9.5 SU PCI DPA Sector Number Register - SUPDSNR ............................ 207
5.10.9.6 SU PCI DPA Cylinder Low Register - SUPDCLR ................................ 208
5.10.9.7 SU PCI DPA Cylinder High Register - SUPDCHR...............................209
5.10.9.8 SU PCI DPA Device/Head Register - SUPDDR .................................. 210
5.10.9.9 SU PCI DPA Status Register - SUPDSR .............................................211
5.10.9.10 SU PCI DPA Command Register - SUPDCR ......................................212
5.10.10 SU PCI DPA Mode Control Block Registers ........................................................ 213
5.10.10.1 SU PCI DPA Alternate Status Register - SUPDASR ........................... 213
5.10.10.2 SU PCI DPA Device Control Register - SUPDDCTLR ........................214
5.10.11 SU PCI DPA Mode DMA Registers .....................................................................215
5.10.11.1 SU PCI DPA Upper DMA Descriptor Table
Pointer Register - SUPDUDDTPR ....................................................... 215
5.10.11.2 SU PCI DPA Upper DMA Data Pointer Register - SUPDUDDBPR .....216
5.10.11.3 SU PCI DPA DMA Command Register - SUPDDCMDR ..................... 217
5.10.11.4 SU PCI DPA DMA Status Register - SUPDDSR ................................. 218
5.10.11.5 SU PCI DPA DMA Descriptor Table Pointer Register - SUPDDDTPR 219
5.10.12 SU PCI DPA Mode Superset Registers ............................................................... 220
5.10.12.1 SU PCI DPA SATA SStatus Register - SUPDSSSR ........................... 220
5.10.12.2 SU PCI DPA SATA SError Register - SUPDSSER ............................. 222
5.10.12.3 SU PCI DPA SATA SControl Register - SUPDSSCR.......................... 225
5.10.12.4 SU PCI DPA Set Device Bits Register - SUPDSDBR.......................... 226
5.10.12.5 SU PCI DPA PHY Feature Register - SUPDPFR ................................ 227
5.10.12.6 SU PCI DPA BIST FIS Control and Status Register - SUPDBFCSR .. 228
5.10.12.7 SU PCI DPA BIST Errors Register - SUPDBER .................................. 231
5.10.12.8 SU PCI DPA BIST Frames Register - SUPDBFR................................ 232
5.10.12.9 SU PCI DPA Host BIST Data Low Register - SUPDHBDLR ............... 233
5.10.12.10SU PCI DPA Host BIST Data High Register - SUPDHBDHR............. 234
5.10.12.11SU PCI DPA Device BIST Data Low Register - SUPDDBDLR........... 235
5.10.12.12SU PCI DPA Device BIST Data High Register - SUPDDBDHR ......... 236
5.10.12.13SU PCI DPA Queuing Table Base Address Register
Low - SUPDQTBARL ........................................................................... 237
5.10.12.14SU PCI DPA Queuing Table Base Address Register
High - SUPDQTBARH ......................................................................... 238
5.10.12.15SU PCI DPA DMA Setup FIS Control and
Status Register - SUPDDSFCSR ........................................................ 239
5.10.12.16SU PCI DPA Host DMA Buffer Identifier
Low Register - SUPDHDBILR.............................................................. 240
5.10.12.17SU PCI DPA Host DMA Buffer Identifier
High Register - SUPDHDBIHR ............................................................ 241
5.10.12.18SU PCI DPA Host Reserved DWORD Register 0 - SUPDHRDR0 .....242
5.10.12.19SU PCI DPA Host DMA Buffer Offset Register - SUPDHDBOR ........ 243
5.10.12.20SU PCI DPA Host DMA Transfer Count Register - SUPDHDTCR .....244
5.10.12.21SU PCI DPA Host Reserved DWORD Register 1- SUPDHRDR1...... 245
Developer’s Manual
April 2004
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