EW31244SL7QV Datasheet, PDF (224/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 136. SU PCI DPA SATA SError Register - SUPDSSER (Sheet 3 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rv rv rv rc rv rv rc rc rc rv rc rv rc rv rv rv rv rc rc rc rc rv rv rv rv rv rv rc rv
PCI IDE Mode BAR5 Offset
= 004H,
DPA Mode BAR0 Offset
Port 0 = 304H, Port 1 = 504H
Port 2 = 704H, Port 3 = 904H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
ERR_M - Recovered Communications Error:
This bit indicates that the PHY went from NOT-READY to READY. This bit shall remain cleared when
the PHY was not detected as ready during the initialization process. When the PHY goes ready after
01
0₂
initialization, this bit shall transition to 1. This bit is cleared by writing a 1 to it. This bit is reported as an
interrupt on bit 1, 9, 17, and 25 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3
respectively. Refer to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready as part of the initialization sequence, the value will change to 1₂.
00
0₂
ERR_I - Reserved, not implemented.
224
April 2004
Developer’s Manual