EW31244SL7QV Datasheet, PDF (69/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.2
Direct Port Access Mode
Figure 23.
This mode is specific to the 31244, it allows an external PCI master to control each SATA port
independently. All four SATA port registers within the Serial ATA Unit are mapped contiguously in
the PCI Memory Space using the PCI Base Address Registers, Section 5.10.7.1, “SU PCI DPA
Base Address Register 0 - SUPDBAR0” on page 192 and Section 5.10.7.2, “SU PCI DPA Upper
Base Address Register 0 - SUPDUBAR0” on page 193. Each SATA port register occupies
512 bytes of space. Figure 23 shows the SATA ports to Base Address Register mapping. All the
four SATA port registers within a Serial ATA Unit occupy 4 Kbytes of space. There is a common
set of registers that are shared by all the SATA ports. Each SATA port consists of the following
register blocks. The SATA ports registers are offset at 200H, 400H, 600H, and 800H for SATA
Port 0, 1, 2, and 3 respectively. The Command Port register space starts at offset 000H.
• Common SATA Port Registers - shared by all SATA ports
• Command Block Registers
• Control Block Registers
• DMA registers
• Superset Registers
SATA Unit Register Mapping in Direct Port Access Mode
Offset
PCI Configuration Space
10H
Base Address Register
14H ^{Upper Base Address Register 0}
31
Common Port Registers
SATA Port 0 Registers
SATA Port 1 Registers
SATA Port 2 Registers
SATA Port 3 Registers
0 Offset
000H
1FFH
200H
3FFH
400H
5FFH
600H
7FFH
800H
9FFH
A00H
512 Bytes
2 Kbytes
(4 x 512 Bytes)
Reserved
1536 Bytes
FFFH
Developer’s Manual
April 2004
69