EW31244SL7QV Datasheet, PDF (250/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.26 SU PCI DPA Device DMA Transfer Count Register - SUPDDDTCR
Table 160.
The SU PCI DPA Device DMA Transfer Count Register is the fifth DWORD parameter of the
SATA DMA Setup Device-to-Host FIS. Refer to the Serial ATA Specification.
SU PCI DPA Device DMA Transfer Count Register - SUPDDTCR
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI IDE Mode Offset
= 094H,
DPA Mode Offset
Port 0 = 394H, Port 1 = 594H
Port 2 = 794H, Port 3 = 994H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
31:00
Default
Description
0000_0000H Transfer Count - The transfer Count field of the First Party Setup FIS.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
250
April 2004
Developer’s Manual