EW31244SL7QV Datasheet, PDF (202/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 117. SU PCI DPA Interrupt Mask Register - SUPDIMR (Sheet 3 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
DPA Mode BAR0 Offset
004H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 1 PHY Ready Interrupt Mask Bit.
09
0₂
0 = Masked
1 = Not Masked
SATA Port 1 PHY Change State Interrupt Mask Bit.
08
0₂
0 = Masked
1 = Not Masked
SATA Port 0 IDE Interrupt Mask Bit.
07
1₂
0 = Masked
1 = Not Masked
SATA Port 0 Signal Detect Interrupt Mask Bit.
06
0₂
0 = Masked
1 = Not Masked
SATA Port 0 Data Integrity Interrupt Mask Bit.
05
0₂
0 = Masked
1 = Not Masked
SATA Port 0 Unrecognized FIS Reception Interrupt Mask Bit.
04
0₂
0 = Masked
1 = Not Masked
SATA Port 0 R_ERR Primitive Received Interrupt Mask Bit.
03
0₂
0 = Masked
1 = Not Masked
SATA Port 0 FIFO Error Interrupt Mask Bit.
02
0₂
0 = Masked
1 = Not Masked
SATA Port 0 PHY Ready Interrupt Mask Bit.
01
0₂
0 = Masked
1 = Not Masked
SATA Port 0 PHY Change State Interrupt Mask Bit.
00
0₂
0 = Masked
1 = Not Masked
202
April 2004
Developer’s Manual