EW31244SL7QV Datasheet, PDF (45/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.9.2
3.1.9.2.1
SPI Command / Control / Status Register - Address 90h
SPI Command
Table 17.
3.1.9.2.2
SPI Command
Master / Slave Mode and Direct Port Access Mode
Bits Type Reset
Description
7:0
r/w
Expansion ROM SPI interface command type. A write to this register
initiates the command. The status register bit D0 must be polled to
determine when the command is complete.
06h = WREN (Write Enable)
04h = WRDI (Write Disable)
01h = WRSR (Write Status)
00h 02h = No action (SPI PROGRAM command)
52h = SECT_ERASE (Sector Erase)
62h = CHIP_ERASE (All Sector Erase)
05h = RDSR (Read Status)
03h = No action (SPI READ command)
15h = RDID (Read ID)
Others = No action
SPI Control
Table 18.
3.1.9.2.3
SPI Control
Bits
15:10
9:8
Type
r/-
r/w
SPI Status
Master / Slave Mode and Direct Port Access Mode
Reset
00h
00b
Description
Reserved.
Sector address [1:0]. Selects one of four sectors for the sector erase
command 52h.
Table 19.
SPI Status
Bits
23:17
Type
r/-
16
r/-
Master / Slave Mode and Direct Port Access Mode
Reset
Description
00h Reserved.
Command done. When HIGH, this indicates that the last command has been
0b communicated to the serial device. It does not indicate the device is ready.
The RDSR command must be issued to determine this.
Developer’s Manual
April 2004
45