EW31244SL7QV Datasheet, PDF (188/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 113.
SATA Port Registers Mapping in PCI DPA Mode (Sheet 4 of 7)
Register Name
SU PCI DPA Host BIST Data Low Register - SUPDHBDLR
SU PCI DPA Host BIST Data High Register - SUPDHBDHR
SU PCI DPA Device BIST Data Low Register - SUPDDBDLR
SU PCI DPA Device BIST Data High Register - SUPDDBDHR
SU PCI DPA Queuing Table Base Address Register Low - SUPDQTBARL
SU PCI DPA Queuing Table Base Address Register High - SUPDQTBARH
SU PCI DPA DMA Setup FIS Control and Status Register - SUPDDSFCSR
SU PCI DPA Host DMA Buffer Identifier Low Register - SUPDHDBILR
SU PCI DPA Host DMA Buffer Identifier High Register - SUPDHDBIHR
SU PCI DPA Host Reserved DWORD Register 0 - SUPDHRDR 0.
SU PCI DPA Host DMA Buffer Offset Register - SUPDHDBOR
Offset
Port 0 - 350H
Port 1 - 550H
Port 2 - 750H
Port 3 - 950H
Port 0 - 354H
Port 1 - 554H
Port 2 - 754H
Port 3 - 954H
Port 0 - 358H
Port 1 - 558H
Port 2 - 758H
Port 3 - 958H
Port 0 - 35CH
Port 1 - 55CH
Port 2 - 75CH
Port 3 - 95CH
Port 0 - 360H
Port 1 - 560H
Port 2 - 760H
Port 3 - 960H
Port 0 - 364H
Port 1 - 564H
Port 2 - 764H
Port 3 - 964H
Port 0 - 368H
Port 1 - 568H
Port 2 - 768H
Port 3 - 968H
Port 0 - 36CH
Port 1 - 56CH
Port 2 - 76CH
Port 3 - 96CH
Port 0 - 370H
Port 1 - 570H
Port 2 - 770H
Port 3 - 970H
Port 0 - 374H
Port 1 - 574H
Port 2 - 774H
Port 3 - 974H
Port 0 - 378H
Port 1 - 578H
Port 2 - 778H
Port 3 - 978H
188
April 2004
Developer’s Manual