EW31244SL7QV Datasheet, PDF (105/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Figure 35. SU in PCI IDE Mode Interface Extended Configuration Header Format (MSI Capability)
MSI Message Control
Reserved
MSI Next Item Pointer MSI Capability ID
MSI Message Address
MSI Message Upper Address
MSI Message Data
F0H
F4H
F8H
FCH
The first byte at the Extended Configuration Offset F0H is the MSI Capability Identifier Register
(Section 5.10.2.50). This will identify this Extended Configuration Header space as the type
defined by the PCI Local Bus Specification, Revision 2.2.
Following the Capability Identifier Register will be the single byte Next Item Pointer Register
(Section 5.10.2.51) which will indicate the configuration offset of an additional Extended
Capabilities Header, when supported. In the SATA Unit, the Next Item Pointer Register is set to
00H indicating that there is no additional Extended Capabilities Headers supported in the SATA
Unit configuration space.
The following sections describe the Serial ATA Unit configuration registers. Configuration space
consists of 8-, 16-, 24-, and 32-bit registers arranged in a predefined format. Each register is described
in functionality, access type (read/write, read/clear, read only) and reset default condition.
See Section 1.2, “Terminology and Conventions” on page 16 for a description of reserved, read
only, and read/clear. All registers adhere to the definitions found in the PCI Local Bus
Specification, Revision 2.2 unless otherwise noted.
The PCI register number for each register is given in Table 35. As stated, a Type 0 configuration
command on the bus with an active IDSEL.
Developer’s Manual
April 2004
105