EW31244SL7QV Datasheet, PDF (79/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.5
Serial ATA BIST
Figure 28.
The Serial ATA Specification identifies three loopback test schemes, of which one is required to be
implemented:
• Far-End Retimed (required feature)
• Far-End Analog (Vendor specific)
• Near-End Analog (Vendor specific)
The GD31244 controller does not support Near-End Analog loopback. The three loopback paths
are shown in Figure 28, Figure 29 and Figure 30. A BIST test may be initiated by either the host or
the device sending the BIST Activate FIS. For example, the BIST Activate FIS is bidirectional.
The BIST Activate FIS contains control bits that indicate the action that the receiver should take
upon receipt of the FIS. The GD31244 controller implements BIST using the SU PCI DPA BIST
FIS Control and Status Register - SUPDBFCSR. For example, this register is used to initiate and
send a BIST Activate FIS to the receiver and is also used to notify the receipt of a BIST Activate
FIS from the far-end device. In addition to the SU PCI DPA BIST FIS Control and Status Register
- SUPDBFCSR, the SU PCI DPA Host BIST Data Low Register - SUPDHBDLR and SU PCI DPA
Host BIST Data High Register - SUPDHBDHR are used for the two data DWORDs of the BIST
Activate FIS. When a BIST FIS is received, the two Data DWORDs are written into the SU PCI
DPA Device BIST Data Low Register - SUPDDBDLR and SU PCI DPA Device BIST Data High
Register - SUPDDBDHR.
Far-End Retimed Loopback Setup
0 TX+*
0 TX-*
RX+* ₁
RX-* 1
Data
Extraction
Block
Fixed
Pattern
Source
Fixed
Pattern
Detect
Analog
Front End
Analog
Front End
Silicon
Loopback
Data
Extraction
Block
1 RX+*
1 RX-*
TX+* ₀
TX-* 0
B1247-01
Developer’s Manual
April 2004
79