EW31244SL7QV Datasheet, PDF (93/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.5 Corrupted or Unexpected Split Completions
Warning:
When any of the errors discussed in this section actually occur, a catastrophic system failure is
likely to result from which the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a
provides no recovery mechanism. In these cases, the GD31244 controller may be communicating
with a non-compliant target device or the system may not be configured properly.
5.6.5.1
Completer Address
The GD31244 controller will assert DEVSEL# for split completion transactions where only the
Requester ID matches that of a currently outstanding split request in the outbound transaction
queue. For example, the Tag does not have to match.
However, the GD31244 controller will discard the data of a split completion with an unmatched
Tag and set the Unexpected Split Completion bit (bit 19) in the SUPCIXSR. The SATA Ports’
DMAs are not halted in this situation.
When the Sequence ID of a split completion transaction matches that of an outstanding request, but
the Lower Address field is not valid, the GD31244 controller will accept the split completion
transaction in its’ entirety according to the invalid Lower Address field as when nothing happened.
5.6.5.2
Completer Attributes
When the Sequence ID of a split completion transaction matches that of an outstanding request, but
the Byte Count is not valid, the GD31244 controller will accept the split completion transaction in
its entirety according to the invalid byte count field as when nothing happened.
Developer’s Manual
April 2004
93